SYSTEM VERILOG FAQ

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We've received a fine selection of FAQs regarding Formal Verification and System Verilog Assertion.

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QUESTIONS:

Which are the most important things to be considered while writing assertions?
What are the types of assertions? Explain them.
What is the difference between Concurrent and Immediate assertions?
What is false negative?
What is false positive?
What are the functionalities of $rose, $fell and $stable ? Give an examples.
Explain the four different layers of concurrent assertions.
What is the difference between goto repetition and non-consecutive repetition? Give an example.
How do you know that you have over constrained the design?
What happens if the design is over-constrained?
How do you know that you have under constrained the design?
What happens if the design is under-constrained?

ANSWERS:

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1. Which are the most important things to be considered while writing assertions? *

2. What are the types of assertions? Explain them. *

3. What is the difference between Concurrent and Immediate assertions? *

4. What is false negative? *

5. What is false positive? *

6. What are the functionalities of $rose, $fell and $stable ? Give an example. *

7. Explain the four different layers of concurrent assertions. *

8. What is the difference between goto repetition and non-consecutive repetition? Give an example. *

9. How do you know that you have over constrained the design? *

10. What happens if the design is over-constrained? *

11. How do you know that you have under constrained the design? *

12. What happens if the design is under-constrained? *

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